A really versatile master clock nodule would be on my wish list.

David Salter
Senior Consultant
PSG

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________________________________

From: Doepfer_a100@yahoogroups.com [mailto: Doepfer_a100@yahoogroups.com ]
On Behalf Of hardware@...
Sent: 28 February 2008 14:07
To: Doepfer_a100@yahoogroups.com
Subject: AW: 1 Re: clock division: am i missing something

> hallo mark,
>
> there are different things that i'm after, but an easy one to follow
> is having several envelopes, one of which should fire off at every
> quarter, one of which at every bar etc. after a reset/start they
> should all fire off on the 1, and then keep going at their respective
> intervals. quite the opposite happens with the a190, since the all the
> gates start off with "off".
>
> to express it in binary terms, directly after a start i have 00000000
> when what i need is 11111111.
>
> this is the reverse of the a190's behaviour. dieter, can this be
> hacked very unlikely, i know, but if you don't ask you don't get :)
>
> cheers,
>
> stu

That's not a problem of the A-190 as it outputs only clock and
start/stop
but has no trigger/gate outputs but the device controlled by the A-190 !

I know the problems you are talking about as I had many years ago a
master
clock unit with a lot of trigger and gate outputs., positive and
negative
edge triggered clock and reset inputs and many more. A bit similar to
the
A-160 and and A-161 but even with inverted and trigger outputs, and
inverted
clock/reset inputs. To emulate these functions several additional
trigger
inverters are required (A-165).

If I understand your problem it could be solved by the A-161 and the
A-186-1
as the A-161 has a separate gate output for each step available. To
solve
the 000/111 problem simply use output #2 of the A-161 as the first gate.
The
outputs of the A-161 can be combined by the A-186-1.

We could develop a master clock module (e.g. a copy of my old device)
but
I'm not sure if there are sufficient inquiries.

Best wishes
Dieter Doepfer






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