Hi Joe,
I had an idea that nearly worked with respect to this:

> thinking. The A163 doesn't have a reset input like the A160 clock
> divider does. Won't it end up in an indeterminate state when you

reset

> the master clock That would mean the clock pulses from the A163

could

> be as much as 180 degrees out of phase with the master clock, a
> half-step delay.
>
> Has anyone tried this Is there any way to do what I want to do

The idea was to hold the 163 at 'divide by 1' whilst in a 'reset'
state, then let it jump back to the required 'divide by n' when the
reset is removed (and which by assumption also re-starts the main
clock). Hopefully this means it starts dividing again from the right
point. I did this by switching the CV controlling the 'divide by n'
through a 150, with the other side at ground, and set the 163 so that
the ground input gave 'divide by 1'. The 'reset' then controls the
150. The 'fly in the ointment' turned out to be a couple of
capacitors having a smoothing effect on the CV input to the 163, so
it cannot see instaneous jumps in CV - it quickly ramps
through 'divide by 2', 'divide by 3' etc. to eventually get
to 'divide by n'. I'm assuming the caps are there for stability
purposes - whether they could be reduced sufficiently to allow this
idea to work (it may not even be a very good one at that!) and still
be stable, I don't know, I'll think some more on it...

Tim